本书共包括11章正文和两篇附录。为了让读者了解传统的人工进行数字设计的基本理论，前六章主要还是介绍数字逻辑的基础，且此部分内容可以作为一个学期的数字逻辑设计导论课程。由于数字系统的规模越来越大，採用计算机辅助设计工具来完成数字电路的设计势在必行，因此本书从第2章开始就将相关知识融入到基础理论中，让读者能在阅读和学习过程中潜移默化地掌握Verilog代码编写风格，达到事半功倍的效果。

Chapter 1Introduction1

1.1Digital Hardware2

1.1.1Standard Chips4

1.1.2Programmable Logic Devices5

1.1.3CustomDesigned Chips5

1.2The Design Process6

1.3Structure of a Computer8

1.4Logic Circuit Design in This Book8

1.5Digital Representation of Information11

1.5.1Binary Numbers12

1.5.2Conversion between Decimal and

Binary Systems13

1.5.3ASCII Character Code14

1.5.4Digital and Analog Information16

1.6Theory and Practice16

Problems18

References19

Chapter 2Introduction to Logic

Circuits21

2.1Variables and Functions22

2.2Inversion25

2.3Truth Tables26

2.4Logic Gates and Networks27

2.4.1Analysis of a Logic Network29

2.5Boolean Algebra33

2.5.1The Venn Diagram37

2.5.2Notation and Terminology42

2.5.3Precedence of Operations43

第1章绪论1

1.1数字硬体2

1.1.1标準晶片4

1.1.2可程式逻辑器件5

1.1.3定製晶片5

1.2设计过程6

1.3计算机结构8

1.4本书中的逻辑电路设计8

1.5信息的数字表示11

1.5.1二进制数12

1.5.2十进制和二进制系统之间的

转换13

1.5.3ASCII字元码14

1.5.4数字和模拟信息16

1.6理论和实践16

习题18

参考文献19

第2章逻辑电路导论21

2.1变数和函式22

2.2反相25

2.3真值表26

2.4逻辑门和网路27

2.4.1逻辑网路的分析29

2.5布尔代数33

2.5.1维恩图37

2.5.2符号和术语42

2.5.3操作的优先权43

2.6Synthesis Using AND, OR, and NOT

Gates43

2.6.1SumofProducts and Productof

Sums Forms48

2.7NAND and NOR Logic Networks54

2.8Design Examples59

2.8.1ThreeWay Light Control59

2.8.2Multiplexer Circuit60

2.8.3Number Display63

2.9Introduction to CAD Tools64

2.9.1Design Entry64

2.9.2Logic Synthesis66

2.9.3Functional Simulation67

2.9.4Physical Design67

2.9.5Timing Simulation67

2.9.6Circuit Implementation68

2.9.7Complete Design Flow68

2.10Introduction to Verilog68

2.10.1Structural Specification of Logic

Circuits70

2.10.2Behavioral Specification of Logic

Circuits72

2.10.3Hierarchical Verilog Code76

2.10.4How NOT to Write Verilog Code78

2.11Minimization and Karnaugh Maps78

2.12Strategy for Minimization87

2.12.1Terminology87

2.12.2Minimization Procedure89

2.13Minimization of ProductofSums Forms91

2.14Incompletely Specified Functions94

2.15MultipleOutput Circuits96

2.16Concluding Remarks101

2.17Examples of Solved Problems101

Problems111

References120

2.6用与、或和非门进行综合43

2.6.1与或和或与形式48

2.7与非和或非逻辑网路54

2.8设计实例59

2.8.1三路灯光控制59

2.8.2多路选择器电路60

2.8.3数字显示63

2.9CAD工具简介64

2.9.1设计输入64

2.9.2逻辑综合66

2.9.3功能仿真67

2.9.4物理设计67

2.9.5时序仿真67

2.9.6电路实现68

2.9.7完整的设计流程68

2.10Verilog简介68

2.10.1逻辑电路的结构描述70

2.10.2逻辑电路的行为描述72

2.10.3层次化Verilog代码76

2.10.4如何不写Verilog代码78

2.11化简和卡诺图78

2.12化简策略87

2.12.1术语87

2.12.2化简过程89

2.13或与形式的最简91

2.14不完全确定函式94

2.15多输出电路96

2.16小结101

2.17问题求解案例101

习题111

参考文献120

Chapter 3Number Representation and

Arithmetic Circuits121

3.1Positional Number Representation122

3.1.1Unsigned Integers122

3.1.2Octal and Hexadecimal

Representations123

3.2Addition of Unsigned Numbers125

3.2.1Decomposed FullAdder129

3.2.2RippleCarry Adder129

3.2.3Design Example130

3.3Signed Numbers132

3.3.1Negative Numbers133

3.3.2Addition and Subtraction135

3.3.3Adder and Subtractor Unit138

3.3.4RadixComplement Schemes139

3.3.5Arithmetic Overflow143

3.3.6Performance Issues145

3.4Fast Adders145

3.4.1CarryLookahead Adder146

3.5Design of Arithmetic Circuits Using CAD

Tools151

3.5.1Design of Arithmetic Circuits Using

Schematic Capture151

3.5.2Design of Arithmetic Circuits Using

Verilog152

3.5.3Using Vectored Signals155

3.5.4Using a Generic Specification156

3.5.5Nets and Variables in Verilog158

3.5.6Arithmetic Assignment

Statements159

3.5.7Module Hierarchy in Verilog

Code163

3.5.8Representation of Numbers in Verilog

Code166

3.6Multiplication167

3.6.1Array Multiplier for Unsigned

Numbers167

3.6.2Multiplication of Signed

Numbers169

3.7Other Number Representations170

3.7.1FixedPoint Numbers170

3.7.2FloatingPoint Numbers172

3.7.3BinaryCodedDecimal

Representation174

3.8Examples of Solved Problems178

Problems184

References188

Chapter 4CombinationalCircuit Building

Blocks189

4.1Multiplexers190

4.1.1Synthesis of Logic Functions Using Multiplexers193

4.1.2Multiplexer Synthesis Using Shannons

Expansion196

4.2Decoders201

4.2.1Demultiplexers203

4.3Encoders205

4.3.1Binary Encoders205

4.3.2Priority Encoders205

4.4Code Converters208

4.5Arithmetic Comparison Circuits208

4.6Verilog for Combinational Circuits210

4.6.1The Conditional Operator210

4.6.2The IfElse Statement212

4.6.3The Case Statement215

4.6.4The For Loop221

4.6.5Verilog Operators223

4.6.6The Generate Construct228

4.6.7Tasks and Functions229

第3章数的表示和算术电路121

3.1数位表示法122

3.1.1无符号整数122

3.1.2八进制数和十六进制数的

表示123

3.2无符号数的加法125

3.2.1全加器的分解129

3.2.2行波进位加法器129

3.2.3设计实例130

3.3有符号数132

3.3.1负数133

3.3.2加法和减法135

3.3.3加法器和减法器单元138

3.3.4基数补码方案139

3.3.5算术溢出143

3.3.6性能问题145

3.4快速加法器145

3.4.1超前进位加法器146

3.5用CAD工具设计算术电路151

3.5.1用原理图编辑工具设计算术

电路151

3.5.2用Verilog设计算术电路152

3.5.3用向量信号155

3.5.4用自动生成语句156

3.5.5Verilog中的线网和变数158

3.5.6算术赋值语句159

3.5.7Verilog中的模组层次化163

3.5.8Verilog中数的表示166

3.6乘法167

3.6.1无符号数的阵列乘法167

3.6.2有符号数的乘法169

3.7其他数的表示170

3.7.1定点数170

3.7.2浮点数172

3.7.3二进制编码的十进制数

表示174

3.8问题求解案例178

习题184

参考文献188

第4章组合电路构件块189

4.1多路选择器190

4.1.1用多路选择器进行逻辑函式

综合193

4.1.2用香农展开进行多路选择器

综合196

4.2解码器201

4.2.1多路分解器203

4.3编码器205

4.3.1二进制编码器205

4.3.2优先编码器205

4.4码制转换器208

4.5算术比较电路208

4.6用Verilog表示组合电路210

4.6.1条件操作符210

4.6.2ifelse语句212

4.6.3case语句215

4.6.4for循环语句221

4.6.5Verilog操作符223

4.6.6生成结构228

4.6.7任务和函式229

4.7Concluding Remarks232

4.8Examples of Solved Problems233

Problems243

References246

Chapter 5FlipFlops, Registers, and

Counters247

5.1Basic Latch249

5.2Gated SR Latch251

5.2.1Gated SR Latch with NAND

Gates253

5.3Gated D Latch253

5.3.1Effects of Propagation Delays255

5.4EdgeTriggered D FlipFlops256

5.4.1MasterSlave D FlipFlop256

5.4.2Other Types of EdgeTriggered

D FlipFlops258

5.4.3D FlipFlops with Clear and

Preset260

5.4.4FlipFlop Timing Parameters263

5.5T FlipFlop263

5.6JK FlipFlop264

5.7Summary of Terminology266

5.8Registers267

5.8.1Shift Register267

5.8.2ParallelAccess Shift Register267

5.9Counters269

5.9.1Asynchronous Counters269

5.9.2Synchronous Counters272

5.9.3Counters with Parallel Load276

5.10Reset Synchronization278

5.11Other Types of Counters280

5.11.1BCD Counter280

5.11.2Ring Counter280

5.11.3Johnson Counter283

5.11.4Remarks on Counter Design283

5.12Using Storage Elements with CAD

Tools284

5.12.1Including Storage Elements in

Schematics284

5.12.2Using Verilog Constructs for Storage

Elements285

5.12.3Blocking and NonBlocking

Assignments288

5.12.4NonBlocking Assignments for

Combinational Circuits293

5.12.5FlipFlops with Clear

Capability293

5.13Using Verilog Constructs for Registers

and Counters295

5.13.1FlipFlops and Registers with

Enable Inputs300

5.13.2Shift Registers with Enable

Inputs302

5.14Design Example302

5.14.1Reaction Timer302

5.14.2Register Transfer Level (RTL)

Code309

5.15Timing Analysis of Flipflop

Circuits310

5.15.1Timing Analysis with Clock

Skew312

5.16Concluding Remarks314

5.17Examples of Solved Problems315

Problems321

References329

Chapter 6Synchronous Sequential

Circuits331

6.1Basic Design Steps333

6.1.1State Diagram333

4.7小结232

4.8问题求解案例233

习题243

参考文献246

第5章触发器、暂存器和计数器247

5.1基本锁存器249

5.2门控SR锁存器251

5.2.1用与非门实现的门控SR

锁存器253

5.3门控D锁存器253

5.3.1传输延时的影响255

5.4边沿触发的D触发器256

5.4.1主从D触发器256

5.4.2其他类型的边沿触发的

D触发器258

5.4.3带清零和置位的D触发器260

5.4.4触发器的时间参数263

5.5T触发器263

5.6JK触发器264

5.7术语小结266

5.8暂存器267

5.8.1移位暂存器267

5.8.2并行存取的移位暂存器267

5.9计数器269

5.9.1异步计数器269

5.9.2同步计数器272

5.9.3可并行置数的计数器276

5.10同步复位278

5.11其他类型的计数器280

5.11.1BCD计数器280

5.11.2环形计数器280

5.11.3约翰森（Johnson）计数器283

5.11.4计数器设计小结283

5.12CAD工具中存储单元的使用284

5.12.1在原理图中加入存储

单元284

5.12.2用Verilog代码实现存储

单元285

5.12.3阻塞和非阻塞赋值288

5.12.4组合电路的非阻塞赋值293

5.12.5具有清零功能的触发器293

5.13用Verilog代码实现暂存器和

计数器295

5.13.1具有使能输入的触发器和

暂存器300

5.13.2具有使能输入的移位

暂存器302

5.14设计案例302

5.14.1反应计时器302

5.14.2暂存器传输级（RTL）

代码309

5.15触发器电路的时序分析310

5.15.1有时钟漂移的时序分析312

5.16小结314

5.17问题求解案例315

习题321

参考文献329

第6章同步时序电路331

6.1基本设计步骤333

6.1.1状态图333

6.1.2State Table335

6.1.3State Assignment336

6.1.4Choice of FlipFlops and Derivation

of NextState and Output

Expressions337

6.1.5Timing Diagram339

6.1.6Summary of Design Steps340

6.2StateAssignment Problem344

6.2.1OneHot Encoding347

6.3Mealy State Model349

6.4Design of Finite State Machines Using

CAD Tools354

6.4.1Verilog Code for MooreType

FSMs355

6.4.2Synthesis of Verilog Code356

6.4.3Simulating and Testing the

Circuit358

6.4.4Alternative Styles of Verilog

Code359

6.4.5Summary of Design Steps When

Using CAD Tools360

6.4.6Specifying the State Assignment in

Verilog Code361

6.4.7Specification of Mealy FSMs Using

Verilog363

6.5Serial Adder Example363

6.5.1MealyType FSM for Serial

Adder364

6.5.2MooreType FSM for Serial

Adder367

6.5.3Verilog Code for the Serial

Adder370

6.6State Minimization372

6.6.1Partitioning Minimization

Procedure374

6.6.2Incompletely Specified FSMs381

6.7Design of a Counter Using the Sequential

Circuit Approach383

6.7.1State Diagram and State Table for a

Modulo8Counter383

6.7.2State Assignment384

6.7.3Implementation Using DType Flip

Flops385

6.7.4Implementation Using JKType Flip

Flops386

6.7.5Example—A Different Counter390

6.8FSM as an Arbiter Circuit393

6.9Analysis of Synchronous Sequential

Circuits397

6.10Algorithmic State Machine (ASM)

Charts401

6.11Formal Model for Sequential

Circuits405

6.12Concluding Remarks407

6.13Examples of Solved Problems407

Problems416

References420

Chapter 7Digital System Design421

7.1Bus Structure422

7.1.1Using TriState Drivers to Implement

a Bus422

7.1.2Using Multiplexers to Implement

a Bus424

7.1.3Verilog Code for Specification of Bus

Structures426

7.2Simple Processor429

7.3A BitCounting Circuit441

7.4ShiftandAdd Multiplier446

7.5Divider455

7.6Arithmetic Mean466

6.1.2状态表335

6.1.3状态分配336

6.1.4触发器的选择以及次态和

输出表达式的推导337

6.1.5时序图339

6.1.6设计步骤小结340

6.2状态分配问题344

6.2.1单热编码347

6.3米利状态模型349

6.4用CAD工具设计有限状态机354

6.4.1摩尔型有限状态机的Verilog

代码355

6.4.2Verilog代码的综合356

6.4.3仿真和测试该电路358

6.4.4另一种风格的Verilog

代码359

6.4.5用CAD工具的设计步骤

小结360

6.4.6在Verilog代码中进行状态

分配361

6.4.7用Verilog代码来描述米利

有限状态机363

6.5串列加法器举例363

6.5.1串列加法器的米利型有限

状态机364

6.5.2串列加法器的摩尔型有限

状态机367

6.5.3串列加法器的Verilog

代码370

6.6状态化简372

6.6.1化简过程的划分374

6.6.2不完全确定的有限状态机381

6.7用时序电路方法设计计数器383

6.7.1模8计数器的状态图和

状态表383

6.7.2状态分配384

6.7.3用D触发器实现385

6.7.4用JK触发器实现386

6.7.5案例——一个不一样的计数器390

6.8用作仲裁器电路的有限状态机393

6.9同步时序电路分析397

6.10算法状态机（ASM）图401

6.11时序电路的形式化模型405

6.12小结407

6.13问题求解案例407

习题416

参考文献420

第7章数字系统设计421

7.1汇流排结构422

7.1.1用三态驱动器实现汇流排422

7.1.2用多路选择器实现汇流排424

7.1.3汇流排结构的Verilog代码

描述426

7.2简单处理器429

7.3位计数电路441

7.4移位相加实现的乘法器446

7.5除法器455

7.6算术平均466

7.7Sort Operation470

7.8Clock Synchronization and Timing

Issues478

7.8.1Clock Distribution478

7.8.2FlipFlop Timing Parameters481

7.8.3Asynchronous Inputs to

FlipFlops482

7.8.4Switch Debouncing483

7.9Concluding Remarks485

Problems485

References489

Chapter 8Optimized Implementation of

Logic Functions491

8.1Multilevel Synthesis492

8.1.1Factoring493

8.1.2Functional Decomposition496

8.1.3Multilevel NAND and NOR

Circuits502

8.2Analysis of Multilevel Circuits504

8.3Alternative Representations of Logic

Functions510

8.3.1Cubical Representation510

8.3.2Binary Decision Diagrams514

8.4Optimization Techniques Based on Cubical

Representation520

8.4.1A Tabular Method for

Minimization521

8.4.2A Cubical Technique for

Minimization529

8.4.3Practical Considerations536

8.5Concluding Remarks537

8.6Examples of Solved Problems537

Problems546

References549

Chapter 9Asynchronous Sequential

Circuits551

9.1Asynchronous Behavior552

9.2Analysis of Asynchronous Circuits556

9.3Synthesis of Asynchronous Circuits564

9.4State Reduction577

9.5State Assignment592

9.5.1Transition Diagram595

9.5.2Exploiting Unspecified NextState

Entries598

9.5.3State Assignment Using Additional

State Variables602

9.5.4OneHot State Assignment607

9.6Hazards608

9.6.1Static Hazards609

9.6.2Dynamic Hazards613

9.6.3Significance of Hazards614

9.7A Complete Design Example616

9.7.1The VendingMachine

Controller616

9.8Concluding Remarks621

9.9Examples of Solved Problems623

Problems631

References635

Chapter 10Computer Aided Design

Tools637

10.1Synthesis638

10.1.1Netlist Generation638

10.1.2Gate Optimization638

10.1.3Technology Mapping640

10.2Physical Design644

10.2.1Placement646

10.2.2Routing647

10.2.3Static Timing Analysis648

7.7排序操作470

7.8时钟同步和时序问题478

7.8.1时钟偏差478

7.8.2触发器的时序参数481

7.8.3触发器的异步输入482

7.8.4开关抖动483

7.9小结485

习题485

参考文献489

第8章逻辑函式的最佳化实现491

8.1多级综合492

8.1.1提取公因子493

8.1.2函式分解496

8.1.3多级与非和或非电路502

8.2多级电路的分析504

8.3逻辑函式的替代表示510

8.3.1立方体表示510

8.3.2二进制决策图514

8.4基于立方体表示的最佳化技术520

8.4.1化简的列表法521

8.4.2立方体化简技术529

8.4.3实际问题考虑536

8.5小结537

8.6问题求解案例537

习题546

参考文献549

第9章异步时序电路551

9.1异步行为552

9.2异步电路分析556

9.3异步电路综合564

9.4状态化简577

9.5状态分配592

9.5.1转移图595

9.5.2未指定次态项的利用598

9.5.3用附加状态进行的状态

分配602

9.5.4单热状态分配607

9.6冒险608

9.6.1静态冒险609

9.6.2动态冒险613

9.6.3冒险的意义614

9.7一个完整的设计实例616

9.7.1自动售货机控制器616

9.8小结621

9.9问题求解案例623

习题631

参考文献635

第10章计算机辅助设计工具637

10.1综合638

10.1.1网表生成638

10.1.2门最佳化638

10.1.3技术映射640

10.2物理设计644

10.2.1布局646

10.2.2布线647

10.2.3静态时序分析648

10.3Concluding Remarks650

References651

Chapter 11Testing of Logic Circuits653

11.1Fault Model654

11.1.1Stuckat Model654

11.1.2Single and Multiple Faults655

11.1.3CMOS Circuits655

11.2Complexity of a Test Set655

11.3Path Sensitizing657

11.3.1Detection of a Specific Fault659

11.4Circuits with Tree Structure661

11.5Random Tests662

11.6Testing of Sequential Circuits665

11.6.1Design for Testability665

11.7内建自测试669

11.7.1内建逻辑块观察器673

11.7.2签字分析675

11.7.3边界扫描676

11.8印製电路板676

11.8.1PCB测试678

11.8.2测试仪器679

11.9小结680

习题680

参考文献683

附录A数的表示和算术电路685

A.1Verilog代码中的文档686

A.2空白符686

A.3Verilog代码中的信号686

A.4标识符687

A.5信号值、数值和参数687

A.5.1参数688

A.6线网和变数类型688

A.6.1线网688

A.6.2变数689

A.6.3存储器690

A.7操作符690

A.8Verilog模组692

A.9门实例化694

A.10并行语句696

A.10.1连续赋值696

A.10.2使用参数697

A.11过程语句698

A.11.1Always和Initial块698

A.11.2ifelse语句700

A.11.3语句顺序701

A.11.4case语句702

A.11.5Casez和Casex语句703

A.11.6Loop语句704

A.11.7组合电路的阻塞和非阻塞赋值对比708

A.12使用子电路709

A.12.1子电路参数710

A.12.2生成能力712

A.13函式和任务713

A.14时序电路716

A.14.1门控D锁存器717

A.14.2D触发器717

A.14.3带复位的触发器718

A.14.4暂存器718

A.14.5移位暂存器720

A.14.6计数器721

A.14.7时序电路实例722

A.14.8摩尔型有限状态机723

A.14.9MealyTypeFiniteState

Machines724

A.15GuidelinesforWritingVerilog

Code725

A.16ConcludingRemarks731

References731

AppendixBImplementation

Technology733

B.1TransistorSwitches734

B.2NMOSLogicGates736

B.3CMOSLogicGates739

B.3.1SpeedofLogicGateCircuits746

B.4NegativeLogicSystem747

B.5StandardChips749

B.5.17400SeriesStandardChips749

B.6ProgrammableLogicDevices753

B.6.1ProgrammableLogicArray

(PLA)754

B.6.2ProgrammableArrayLogic

(PAL)757

B.6.3ProgrammingofPLAsand

PALs759

B.6.4ComplexProgrammableLogic

Devices(CPLDs)761

B.6.5FieldProgrammableGate

Arrays764

B.7CustomChips,StandardCells,andGate

Arrays769

B.8PracticalAspects771

B.8.1MOSFETFabricationand

Behavior771

B.8.2MOSFETOnResistance775

B.8.3VoltageLevelsinLogicGates776

B.8.4NoiseMargin778

B.8.5DynamicOperationofLogic

Gates779

B.8.6PowerDissipationinLogic

Gates782

B.8.7Passing1sand0sThrough

TransistorSwitches784

B.8.8TransmissionGates786

B.8.9FaninandFanoutin

LogicGates788

B.8.10TristateDrivers792

B.9StaticRandomAccessMemory

(SRAM)794

B.9.1SRAMBlocksinPLDs797

B.10ImplementationDetailsforSPLDs,

CPLDs,andFPGAs797

B.10.1ImplementationinFPGAs804

B.11ConcludingRemarks806

B.12ExamplesofSolvedProblems807

Problems814

References823

Answers825

Index839

A.14.9米利型有限状态机724

A.15编写Verilog代码的原则725

A.16小结731

参考文献731

附录B实现技术733

B.1电晶体开关734

B.2NMOS逻辑门736

B.3CMOS逻辑门739

B.3.1逻辑门电路的速度746

B.4负逻辑系统747

B.5标準晶片749

B.5.17400系列标準晶片749

B.6可程式逻辑器件753

B.6.1可程式逻辑阵列（PLA）754

B.6.2可程式阵列逻辑（PAL）757

B.6.3PLA和PAL的编程759

B.6.4複杂可程式逻辑阵列

（CPLDs）761

B.6.5现场可程式门阵列764

B.7定製晶片、标準单元和门阵列769

B.8实践方面771

B.8.1MOSFET工艺和行为771

B.8.2MOSFET导通电阻775

B.8.3逻辑门中的电平值776

B.8.4噪声容限778

B.8.5逻辑门的动态特性779

B.8.6逻辑门的功耗782

B.8.7通过电晶体开关传输

1和0784

B.8.8传输门786

B.8.9逻辑门的扇入和扇出788

B.8.10三态驱动器792

B.9静态随机存取存储器（SRAM）794

B.9.1PLD中的SRAM块797

B.10SPLD、CPLD和FPGA的实现

细节797

B.10.1FPGA实现804

B.11小结806

B.12问题求解案例807

习题814

参考文献823

习题答案825

索引839